1. Field of the Invention
This invention relates to the field of metal-oxide-semiconductor (MOS) fabrication, and more particularly to a process for forming a reoxidation layer over a gate element during the fabrication of complementary metal-oxide-semiconductor (CMOS) devices.
2. Prior Art
In the manufacture of metal-oxide-semiconductor field effect transistors (MOSFETs), a technique of using tungsten to form a silicide is well-known in the prior art. These metallic silicides, and more specifically tungsten silicide (WSi), are deposited above a polysilicon layer to form a gate member. A silicide layer is used in the gate member to provide a better contact between the gate member and interconnection lines which interconnect the gate member to various other elements of the device. Typically, these interconnection lines are fabricated from aluminum.
In the manufacture of these MOSFET devices, a polysilicon layer is formed over a dielectric layer, such as an oxide, and the silicide layer is deposited over the polysilicon layer to form a gate member. Then, source and drain regions are formed. In one process using a lightly doped drain technique, a first oxide layer is formed over the gate member, a CVD spacer oxide is deposited and various photolithographic and etching techniques are used to shape the gate region for forming lightly doped drain and source regions. The drain and source regions are doped by known techniques, such as by using implantation techniques. Then the oxide spacer layer is removed exposing the silicide portion of the gate member. One such lightly doped technique is described in copending application Ser. No. 926,733 filed Nov. 4, 1986 now U.S. Pat. 4,728,617; and titled "Method of fabricating a MOSFET with graded source and drain regions". Then prior to the deposition of subsequent upper layers, such as the interdielectric layer, a reoxidation technique is used to form a second oxide (reoxidation) layer over the gate member. A reoxidation layer is used in order to ensure good gate edge quality to obtain higher gate edge oxide breakdown voltage, as well as annealing the source and drain dopants. A popular technique is to grow a silicon dioxide (SiO.sub.2) layer over the silicide gate member in which silicon atoms are supplied by the silicide layer because it is silicon rich as deposited and combine with the oxygen atoms to grow a SiO.sub.2 layer over the gate member.
Various prior art techniques describe methods of providing the technique of forming the first oxidation:
(1). "One-Micron Polycide (WSi.sub.2 on Poly-Si) MOSFET Technology"; M. Y. Tsai et al; Journal of Electrochem. Soc.; Solid State Science and Technology; October 1981; pp. 2207-2214.
(2). "Oxidation mechanisms in WSi.sub.2 thin films"; S. Zirinsky et al; Appl.Phys.Lett., 33(1); American Institute of Physics; July 1, 1978; pp. 76-78.
(3). "Kinetics of the thermal oxidation of WSi.sub.2 "; F. Mohammadi et al; Appl.Phys.Lett.; Vol. 35, No. 7; Oct. 1, 1979; pp. 529-531.
However, at the reoxidation step, the silicide film will exhibit a rough textured surface and further causes a non-uniform concentration of tungsten atoms which is supplied by the silicide when Si is not present in an oxidized ambient. As the reoxidation layer is grown over the oxidized silicide, a rough textured oxide deposit is formed above the silicide region of the gate member instead of a smooth planarized surface. In many instances curved "horns" form over the gate member. The non-planarized surface makes it difficult, and in some instances impossible, to form subsequent layers on the silicide portion of the gate member.
To alleviate this problem, one disclosed technique implants phosphorus into the silicide layer to pretreat the silicide prior to the reoxidation occurring. One such technique is disclosed in (4) "CVD WSix Oxidation Characteristics with Ion Implantation Method"; M. Ayukawa et al; V-MIC Conf., IEEE; June 15-16, 1987; pp. 314-320. However, the phosphorus implantation technique disclosed in Reference 4 is not compatible for use in the fabrication of CMOS devices because of the presence of p-channel transistors in a CMOS device.
Therefore, what is required is a reoxidation technique for forming a reoxidation layer over a silicide region of a gate member wherein this technique can be used with a CMOS device which is comprised of both n-channel and p-channel transistors.